The present disclosure relates generally to forming an integrated circuit device on a substrate and, more particularly, to fabricating a decoupling capacitor as part of an integrated circuit.
Integrated circuit (IC) technology generally needs a relatively stable supply voltage that remains within predefined limits. However, an IC typically includes a large number of switches that may rapidly open and close, and such high speed switching may result in transient currents that cause variations in the supply voltage.
To minimize these variations and maintain proper circuit operation, decoupling capacitors may be used to filter at least some of the noise that may be present between operating supplies (e.g., power (Vdd) and ground (Vss)). The decoupling effect of such a capacitor serves to “smooth out” ripples (e.g., waves or pulses) in the operating voltage. Any ripples in the voltage are passed to ground, while direct current (DC) is passed through to the IC's components. When the capacitor is connected across the IC, a transmission line is created with an impedance of Z=(L/C) ½, where ‘L’ is the inductive component and ‘C’ is the capacitive component. As illustrated by the above equation, increasing the capacitive component (by using a larger capacitor, for example) provides better decoupling. 
Decoupling capacitors may be fabricated from large area thin gate oxide capacitors because such capacitors may achieve a relatively high capacitance per unit area. While this type of capacitor may provide decoupling, it also has a number of drawbacks. For example, because thin gate oxide capacitors generally need a relatively large active area, a large die area (e.g., as much as 20-50% of the die area) may be consumed to realize each decoupling capacitor. Furthermore, such large area capacitors are prone to stress failure, thereby limiting yield and/or reliability. For example, if the oxide layer of the capacitor is not thick enough, a stress point may develop and, with time, may cause the capacitor to fail. Alternatively, the capacitor may fail immediately if the oxide layer has a thin hole or other defect. In addition, a large semiconductor resistance may result in a considerable RC time constant, preventing larger capacitors from performing satisfactorily at higher frequencies (e.g., 100 MHz).
In addition to the need for decoupling, electrostatic discharge (ESD) is generally an important issue for ICs. An ESD is generated by a high field potential, which causes ‘charge-and-discharge’ events (e.g., a rapid flow of electrons between two bodies of unequal charge or between one charged body and ground, with an electronic circuit being the path of least resistance between the two). An ESD may damage an IC by causing leakage currents or functional failures, and may even destroy an IC.
Various ESD simulation models exist, including the Human Body Model (HBM) and the Machine Model (MM). Since the human body has a charge-storage capacitance and a highly conductive sweat layer, the discharge from a person's touch may be simulated with the HBM using a resistor-capacitor (or RC) circuit. A IC device should generally survive an ESD of 2000V or higher with the HBM. The MM uses an ESD simulation test based on a discharge network consisting of a charged capacitor and (nominally) zero ohms of series resistance to approximate the electrostatic discharge from a machine. An IC device should generally survive an ESD of 200V or higher with the Machine Model.
Decoupling capacitors that are used to reduce coupling (e.g., Vdd and Vss power noise) may result in strong current spikes and thus degrade ESD performance. Furthermore, Vdd pad areas on commonly used decoupling capacitors, such as thin oxide capacitors, that occupy a large active area may fail at undesirably low ESD levels. For example, a conventional pad structure without a decoupling capacitor may have tested values of HBM 7.5 KV and MM 350V. However, when the pad structure is associated with a decoupling capacitor, the tested voltages at which an IC fails using the HBM and MM may be reduced to less than the desired ESD voltage levels.
Therefore, what is needed is a decoupling capacitor that combines decoupling with improved ESD resistance.